BULLETIN
of the
POLISH ACADEMY of SCIENCES TECHNICAL SCIENCES |
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Volume
57, Issue 3, September 2009
Modeling and optimization of manufacturing systems |
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Issue Index | Authors Index | Scope Index | Web Info | |
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Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files | mirror: http://fluid.ippt.gov.pl/~bulletin/ |
pp 281 - 288 |
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Deadlock freeness supervisor for marked graph |
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H. SIOUD, Z. ACHOUR, A. SAVA, and N. REZG |
This note presents a control synthesis approach for discrete event systems modeled by marked graphs with uncontrollable transitions. The forbidden behavior is specified by General Mutual Exclusion Constraints (GMEC). We prove that, even if the system to be controlled is live, the closed loop control may generate deadlock situations. Using the structural proprieties of marked graph we defined the causes of deadlock situations, and we defined a formal method to avoid them. |
Key words: |
discrete-event system, forbidden state problem, deadlock avoidance, marked graph |
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Issue Index | Authors Index | Scope Index | Web Info |
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Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files |
Copyright
® Bulletin of the Polish Academy of Sciences: Technical Sciences
October 2009 |
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