BULLETIN of the

POLISH ACADEMY of SCIENCES

TECHNICAL SCIENCES

BULLETIN of the POLISH ACADEMY of SCIENCES: TECHNICAL SCIENCES
Volume 57, Issue 3, September 2009

Modeling and optimization of manufacturing systems

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pp 281 - 288

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Deadlock freeness supervisor for marked graph

H. SIOUD, Z. ACHOUR, A. SAVA, and N. REZG
This note presents a control synthesis approach for discrete event systems modeled by marked graphs with uncontrollable transitions. The forbidden behavior is specified by General Mutual Exclusion Constraints (GMEC). We prove that, even if the system to be controlled is live, the closed loop control may generate deadlock situations. Using the structural proprieties of marked graph we defined the causes of deadlock situations, and we defined a formal method to avoid them.
Key words:

discrete-event system, forbidden state problem, deadlock avoidance, marked graph


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Copyright ® Bulletin of the Polish Academy of Sciences: Technical Sciences

October 2009