POLISH ACADEMY of SCIENCES
TECHNICAL SCIENCES
Civil Engineering and Electronics
| BULLETIN
of the
POLISH ACADEMY of SCIENCES TECHNICAL SCIENCES |
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| Volume
54, Issue 4, December 2006
Civil Engineering and Electronics |
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| Issue Index | Authors Index | Scope Index | Web Info | |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files | mirror: http://fluid.ippt.gov.pl/~bulletin/ |
| pp 489 - 498 |
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BDD-based decompositions of multiple output logic functions |
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| A. DZIKOWSKI and E. HRYNKIEWICZ |
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The paper presents modification of the method dedicated to a complex area decomposition of a set of logic functions whereas the altered method is dedicated to implement the considered logic circuits within FPGA structures. The authors attempted to reach solutions where the number of configurable logic blocks and the number of structural layer would be reasonably balanced on the basis of the minimization principle. The main advantage of the procedure when the decomposition is carried out directly on the BDD diagram is the opportunity of immediate checking whether the decomposed areas of the diagram do not exceed the resources of logic blocks incorporated into the integrated circuits that are used for implementation of the logic functions involved. |
| Key words: |
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Binary Decision Diagrams, decomposition, FPGA |
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| Copyright
® Bulletin of the Polish Academy of Sciences: Technical Sciences
9 January 2007, site prepared by KZ |
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