POLISH ACADEMY of SCIENCES
TECHNICAL SCIENCES
Civil Engineering and Electronics
| BULLETIN
of the
POLISH ACADEMY of SCIENCES TECHNICAL SCIENCES |
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| Volume
54, Issue 4, December 2006
Civil Engineering and Electronics |
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| Issue Index | Authors Index | Scope Index | Web Info | |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files | mirror: http://fluid.ippt.gov.pl/~bulletin/ |
| pp 479 - 487 |
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FSMs state encoding targeting at logic level minimization |
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| R. CZERWINSKI, D. KANIA, and J. KULISZ |
| The paper concerns the problem of state assignment for finite state machines (FSM), targeting at PAL-based CPLDs implementations. Presented in the paper approach is dedicated to state encoding of fast automata. The main idea is to determine the number of logic levels of the transition function before the state encoding process, and keep the constraints during the process. The number of implicants of every single transition function must be known while assigning states, so elements of two level minimization based on Primary and Secondary Merging Conditions are implemented in the algorithm. The method is based on code length extraction if necessary. In one of the most basic stages of the logic synthesis of sequential devices, the elements referring to constraints of PAL-based CPLDs are taken into account. |
| Key words: |
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state assignment, finite state machines (FSM), programmable array logic (PAL), complex programmable logic devices (CPLD) |
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| Issue Index | Authors Index | Scope Index | Web Info |
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| Aims&Scope, Subscription | Editors | Authors' guide | to read PDF files |
| Copyright
® Bulletin of the Polish Academy of Sciences: Technical Sciences
9 January 2007, site prepared by KZ |
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